Certain types of memory systems use a source synchronous clocking scheme to transmit data between the memory controller and the memory device. The use of a source synchronous clocking scheme basically means that during reads, the memory device sources the clock signal and the data, and during writes, the memory controller sources the clock signal and the data. A source synchronous clocking scheme is contrasted with a clocking scheme that uses a single unidirectional clock to determine the sampling point for both transmit data and receive data. Source synchronous clocking schemes are generally used to eliminate timing uncertainties between the data and the clock strobe signal to which the data is timed. Source synchronous clocking schemes can therefore achieve much higher system clock frequencies.
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) is an example of a memory system that uses a source synchronous clocking scheme. During a read operation, a DDR SDRAM generates a data clock strobe signal having edges that are aligned with changes in the read data. A DDR SDRAM transfers data on each rising and falling edge of a clock strobe signal. A DDR SDRAM therefore transfers two data words per clock cycle. A memory controller is often used to coordinate the transfer of data to and from a DDR SDRAM.
Within the memory controller there resides a physical interface or “PHY layer” that interfaces directly with the external DDR SDRAM devices. One of the main functions of the DDR PHY is to capture read data. The memory controller uses the clock strobe signal for determining when the read data is valid and can therefore be captured. The times at which the read data is captured are preferably synchronized to the clock strobe signal so as to capture the read data in the middle of the valid data window or “data eye”.
The data and the clock strobe signal are coincident as they are launched from the DDR SDRAM device. Based on this assumption, the PHY interface of the memory controller delays the clock strobe signal (such as by 90 degrees) through a delay line such that its transitions line up with the middle of the data valid window. The amount of delay provided by the delay line can vary with process, voltage and temperature changes. Therefore, the delay line is preferably programmable such that the settings of the delay line can be adjusted in response to these variances to make the propagation delay through the delay line a proper duration relative to a reference clock.
In the past, this function has been performed by a software routine that is run while the memory device is “off-line”. The software routine measures the period of the reference clock through a calibration circuit and sets the appropriate delay as a function of the reference clock period.
A typical calibration circuit uses an analog or digital delay lock loop (DLL) for calibrating the delay setting to the reference clock. Current DLL circuits include a slave delay line having multiple, cascaded delay cells which, when set properly, have a total propagation delay that is equal to the period of the reference clock. A circuit compares the phases of the rising edges of the reference clock with the phase of the output from the DLL and then adjusts the delay setting in the DLL so that the delay is equal to the period of the reference clock. At this point, the delay through each slave delay cell equals a desired fraction of the reference clock period. The delay setting for the slave delay line can then be used to delay the clock strobe signal by an initial, desired fractional amount of the reference clock.
As mentioned above, the memory device is typically taken “off-line” in order to run the calibration routine and update the delay settings to account for delay variances due to changes in voltage or temperature. This prevents the change in the delay settings from interfering with any currently executing memory accesses. However if the delay settings are updated frequently to keep up with ongoing changes in voltage and temperature, such interruptions can significantly reduce the bandwidth of the memory device.
Improved methods and apparatus are therefore desired for updating data capture delay settings in source synchronous memory systems.